As integrated circuits become faster and denser, requirements for control of topographical features such as planarity, shape, and thickness become increasingly stringent. The necessity for verifying that a given wafer is sufficiently planar and within specifications, i.e. in qualifying and selecting wafers even before processing begins or during processing, is becoming ever greater. A critical component in the characterization of wafers is the wafer topography, sometimes termed substrate geometry.
Wafer topography (i.e., substrate geometry) can be described according to traditional parameters such as shape, thickness/flatness, and nanotopography (NT). These parameters have different characteristics, which are defined in detail in SEMI standards M1, Appendices 1 and 2. SEMI standards M1 is hereby incorporated by reference in its entirety. Note that shape and flatness tend to be low frequency component descriptions of a wafer. Nanotopography is defined in (SEMI standards M41) as the non-planar deviation of the whole front wafer surface within a spatial wavelength range of app. 0.2 to 20 mm and within the fixed quality area. NT features may occur as point, line, or area features. Examples of point features are dimples; examples of area features are epi pins or crowns, bumps on notches or lasermarks; examples of line features are: saw marks from slicing, scratches, slip lines, dopant striation or other process signatures. The individual front/back surface nanotopography of a wafer substrate is typically obtained from the front/back topography by applying high pass filtering schemes such as Double Gaussian (DG) filtering to the topography data, which suppresses the low frequency components of the wafer topography. The substrate NT features are seen to affect the lithography process, for example by contributing to defocus and overlay errors. Characterization and quantification of higher order components of shape and more localized shape features are described in PCT publication No. WO 2010/025334, U.S. Provisional application No. 61/092,720, and U.S. application Ser. No. 12/778,013 all of which are incorporated by reference in their entireties.
As integrated circuit technology progresses to smaller nodes, i.e., as design rules get smaller, localized topography qualification of both wafer front and back surfaces is gaining interest. These localized, higher frequency topographic features in general cannot be fully corrected by lithography scanners. Therefore these features can cause localized defocus and overlay errors, and ultimately lower the yield. A special type of quantification methodology for localized geometry characterization also called Localized Feature Metrics (LFM) has been recently developed by KLA-Tencor. This methodology is effective in detecting and quantifying several types of yield limiting features on wafer surfaces. Prior methodologies of NT characterization are optimized for full wafer characterization, and are limited in accurately capturing and quantifying localized regions of interest. LFM is described in U.S. patent application Ser. No. 12/986,176 by Haiguang Chen et al. application Ser. No. 12/986,176 is hereby incorporated by reference in its entirety. Improvement of accuracy and sensitivity of LFM measurements and analysis is important for advanced nanotopography applications.